This application claims priority to Italian Patent Application Serial No. RM2002A000236, filed Apr. 30, 2002, entitled xe2x80x9cBAND-GAP VOLTAGE REFERENCE,xe2x80x9d which is commonly assigned.
The present invention relates generally to integrated circuits and in particular the present invention relates to low power/low voltage band-gap voltage reference circuits.
Integrated circuits often contain voltage reference circuits to provide a stable reference voltage for use with internal circuit operations. The voltage reference circuit is key in many integrated circuits (ICs) and memories where it is vital to have a stable reference voltage for use in many other circuits of the IC or memory. One such commonly used voltage reference is the band-gap voltage reference circuit.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called xe2x80x9cerase blocksxe2x80x9d. Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
ICs and memories are designed to operate over a set range of supply voltages and temperatures. In modern ICs and memories the supply voltages have become increasingly smaller, which in part decreases the power usage in these circuits. A number of variations of the band-gap voltage reference circuit are available in the art to compensate the band-gap reference circuit over the ranges of operating temperatures. However, these circuits become less effective at compensation as the supply voltage gets lower. An example of this is in modern Flash memories where the operating voltage is 1.65V and the operating temperature range is xe2x88x9240xc2x0 C. to 85xc2x0 C. The situation is even more problematic in portable devices as total power used becomes more of an issue and the band-gap voltage reference circuit must draw as little current as possible (typically no more than 10 xcexcA). Further compounding the issue is the fact that band-gap voltage references typically utilize bipolar junction transistors (BJTs) in their circuits and many of the ICs and memories that they are implemented in do not natively offer high quality BJTs in the underlying integrated circuit technology they are manufactured in.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved compensated band-gap voltage in modern ICs and memory circuits.
The above-mentioned problems with operating, manufacturing, and temperature compensating band-gap voltage reference devices in a modern low power or low voltage IC or memory device are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a band-gap voltage reference includes a current mirror coupled to an upper power rail, a first bipolar junction transistor having a collector coupled to the current mirror through a first resistor, and an emitter coupled to a lower power rail, a second bipolar junction transistor having a collector coupled to the current mirror, and a base coupled to a base of the first bipolar transistor, a second resistor coupled between an emitter of the second bipolar junction transistor and the lower power rail, and an amplifier circuit having an input coupled to the collector and an output coupled to the base of the first bipolar junction transistor.
In another embodiment, an integrated circuit includes a first internal circuit with an output, a second internal circuit with an input, and a band-gap voltage reference coupled to the output of the first internal circuit and a voltage reference output of the band-gap voltage reference coupled to the input of the second internal circuit. The band-gap voltage reference includes a current mirror coupled to a first power rail, a first bipolar junction transistor having a collector coupled to the current mirror through a first resistor, and an emitter coupled to a second power rail, a voltage reference output coupled to the first resistor and to the current mirror, a second bipolar junction transistor having a collector coupled to the current mirror, and a base coupled to a base of the first bipolar transistor, a second resistor coupled between an emitter of the second bipolar junction transistor and the second power rail, and an amplifier circuit having an input coupled to the collector of the first bipolar junction transistor and an output coupled to the base of the first bipolar junction transistor.
In yet another embodiment, a band-gap voltage reference includes a current mirror circuit, a first NPN bipolar junction transistor having a collector coupled to a drain of a first PMOS transistor of the current mirror circuit through a first resistor, and an emitter coupled to a second power rail, a second NPN bipolar junction transistor that has a base-emitter junction area that is larger than a base-emitter junction area of the first NPN bipolar junction, having a collector coupled to a drain of a second PMOS transistor of the current mirror circuit, and a base of the second NPN bipolar junction transistor coupled to a base of the first NPN bipolar transistor, a second resistor coupled between an emitter of the second NPN bipolar junction transistor and the second power rail, and an amplifier circuit. The current mirror circuit includes a first PMOS transistor having a source coupled to a first power rail, and a second PMOS transistor having a source coupled to the first power rail and a gate of the second PMOS transistor coupled a drain of the second PMOS transistor and to a gate of the first PMOS transistor. The amplifier circuit has an input coupled to the collector of the first NPN bipolar junction transistor and an output coupled to the base of the first NPN bipolar junction transistor. The amplifier circuit includes a capacitor coupled between the input and the output, a third NPN bipolar junction transistor having a base coupled to the input through a third resistor, and an emitter coupled to the second power rail, a NMOS transistor having a source coupled to the second power rail through a fourth resistor, a gate coupled to a collector of the third NPN bipolar junction transistor, and a drain coupled to the output, a third PMOS transistor having a source coupled to the first power rail, a gate coupled to the gate of the second PMOS transistor of the current mirror circuit, and a drain coupled to the collector of the third NPN bipolar junction transistor, and one or more fourth PMOS transistors having a source of each of the one or more fourth PMOS transistors coupled to the first power rail, a gate of each of the one or more fourth PMOS transistors coupled to the gate of the second PMOS transistor of the current mirror circuit, and a drain of the one or more fourth PMOS transistors coupled to the output.
In a further embodiment, a non-volatile memory includes a non-volatile memory array, a controller circuit, and at least one band-gap voltage reference. The at least one band-gap voltage reference includes a current mirror coupled to a positive power rail, a first bipolar junction transistor having a collector coupled to the current mirror through a first resistor, and an emitter coupled to a negative power rail, a second bipolar junction transistor having a collector coupled to the current mirror, and a base coupled to a base of the first bipolar transistor, a second resistor coupled between an emitter of the second bipolar junction transistor and the negative power rail, and an amplifier circuit having an input coupled to the collector and an output coupled to the base of the first bipolar junction transistor.
In yet a further embodiment, a method of operating a band-gap voltage reference that includes a current mirror coupled to an upper power rail, a first bipolar junction transistor having a collector coupled to the current mirror through a first resistor, and an emitter coupled to a lower power rail, a second bipolar junction transistor having a collector coupled to the current mirror, and a base coupled to a base of the first bipolar transistor, a second resistor coupled between an emitter of the second bipolar junction transistor and the lower power rail, and an amplifier circuit having an input coupled to the collector and an output coupled to the base of the first bipolar junction transistor, includes operating the amplifier circuit to provide an amplified current from the collector of the first bipolar junction transistor to the base of the first bipolar junction transistor.